Pattern Generation for Composite Leakage Current Maximization

There are three major sources of leakage current today, namely the sub-threshold leakage, gate leakage and the reverse biased junction band-to-band-tunneling leakage. These currents depend on the logic state of a CMOS circuit as determined by input pattern. Consequently, there exists a pattern that will produce the highest leakage current. Previously, researchers have investigated the problem of finding such a pattern for maximizing sub-threshold leakage current. A pattern that maximizes sub-threshold leakage may not maximize the overall leakage current. In this paper, we consider all leakage sources together and try to find an input pattern(s) that will maximize the composite leakage current made up of all three components. The computation involves Boolean reasoning on a pre-characterized set of interconnected gates. This problem is known to be computationally intractable. We used a target based approach to reduce the complexity. This paper describes the (i) formulation of the search problem based on actual leakage values computed from Berkeley Predictive Technology Model for 65nm and 45nm technologies, (ii) a solution to the search problem and (iii) the results from our investigation. Keywords-sub-threshold leakage, gate leakage, BTBT leakage, current maximization, branch and bound heuristic